![PDF] A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/98bc7aca1b3f15db97ef2f3e50dcc030bd05c29e/2-Figure1-1.png "PDF] A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC | Semantic Scholar")
PDF] A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC | Semantic Scholar
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